1 Yozshuzshura

Non-Blocking Assignment Systems Control

The term Blocking assignment confuses people because the word blocking would seem to suggest time-sequential logic. But in synthesized logic it does not mean this, because everything operates in parallel.

Perhaps a less confusing term would be immediate assignment, which would still differentiate the intermediate results of combinational logic from the inputs to non-transparent memory elements (for example clocked registers), which can have delayed assignment.

From a legalistic standpoint, it all works out very nicely. You can, in fact, consider the to be a blocking (time-sequential) operation even within sequences. However, the distinction between time-sequential and parallel makes absolutely no difference in this case because the block is defined to repeat until the instruction sequence converges on a stable state -- which is exactly what the hardware circuitry will do (if it meets the timing requirements).

The synthesizable subset of Verilog (and especially SystemVerilog) is extremely simple and easy to use -- once you know the necessary idioms. You just have to get past the clever use of terminology associated with the so-called behavioral elements in the language.

answered Jan 10 '15 at

LRM says: The always_ff procedure imposes the restriction that it contains one and only one event control and no blocking timing controls. Variables on the left-hand side of assignments within an always_ff procedure, including variables from the contents of a called function, shall not be written to by any other process.

Software tools should perform additional checks to warn if the behavior within an always_ff procedure does not represent sequential logic.

A blocking assignment is not a blocking timing control. Blocking timing controls are #, @, wait, and task calls. Thus,
always_ff @(posedge clk) begin // LEGAL
logic temp;
temp=a && b; // local evaluation, for later usage
if(temp) c <= d;

always_ff @(posedge clk) begin // ILLEGAL
logic temp;
#1 // <<<< ILLEGAL
temp=a && b; // local evaluation, for later usage
if(temp) e <= d;

Ben Cohen ()
* SystemVerilog Assertions Handbook, 2nd Edition, ISBN
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* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, , ISBN
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